<small>Processors Information</small> |
<small><small> </small></small> |
<small>Processor 1</small> |
<small>ID = 0</small> |
<small> Number of cores</small> |
<small>2 (max 8)</small> |
<small> Number of threads</small> |
<small>4 (max 16)</small> |
<small> Name</small> |
<small>Intel Core i5</small> |
<small> Codename</small> |
<small>Ivy Bridge</small> |
<small> Specification</small> |
<small>Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz</small> |
<small> Package (platform ID)</small> |
<small>Socket 988B rPGA (0x4)</small> |
<small> CPUID</small> |
<small>6.A.9</small> |
<small> Extended CPUID</small> |
<small>6.3A</small> |
<small> Core Stepping</small> |
<small>E1</small> |
<small> Technology</small> |
<small>22 nm</small> |
<small> TDP Limit</small> |
<small>35 Watts</small> |
<small> Core Speed</small> |
<small>1197.3 MHz</small> |
<small> Multiplier x FSB</small> |
<small>12.0 x 99.8 MHz</small> |
<small> Stock frequency</small> |
<small>2500 MHz</small> |
<small> Instructions sets</small> |
<small>MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, EM64T, AES, AVX</small> |
<small> L1 Data cache</small> |
<small>2 x 32 KBytes, 8-way set associative, 64-byte line size</small> |
<small> L1 Instruction cache</small> |
<small>2 x 32 KBytes, 8-way set associative, 64-byte line size</small> |
<small> L2 cache</small> |
<small>2 x 256 KBytes, 8-way set associative, 64-byte line size</small> |
<small> L3 cache</small> |
<small>3 MBytes, 12-way set associative, 64-byte line size</small> |
<small> FID/VID Control</small> |
<small>yes</small> |
<small> </small> |
<small> </small> |
<small> </small> |
<small> </small> |
<small> Turbo Mode</small> |
<small>supported, enabled</small> |
<small> Max non-turbo ratio</small> |
<small>25x</small> |
<small> Max turbo ratio</small> |
<small>31x</small> |
<small> Max efficiency ratio</small> |
<small>12x</small> |
<small> Min Power</small> |
<small>24 Watts</small> |
<small> O/C bins</small> |
<small>none</small> |
<small> Ratio 1 core</small> |
<small>31x</small> |
<small> Ratio 2 cores</small> |
<small>29x</small> |
<small> Ratio 3 cores</small> |
<small>29x</small> |
<small> Ratio 4 cores</small> |
<small>29x</small> |
<small> TSC</small> |
<small>2494.4 MHz</small> |
<small> APERF</small> |
<small>2979.3 MHz</small> |
<small> MPERF</small> |
<small>2480.1 MHz</small> |
<small> </small> |
<small> </small> |
<small> </small> |
<small> </small> |
<small> </small> |
<small> </small> |
<small>Chipset</small> |
<small><small> </small></small> |
<small>Northbridge</small> |
<small>Intel Ivy Bridge rev. 09</small> |
<small>Southbridge</small> |
<small>Intel HM77 rev. 04</small> |
<small>Memory Type</small> |
<small>DDR3</small> |
<small>Memory Size</small> |
<small>8192 MBytes</small> |
<small>Channels</small> |
<small>Dual</small> |
<small>Memory Frequency</small> |
<small>798.3 MHz (1:6)</small> |
<small>CAS# latency (CL)</small> |
<small>11.0</small> |
<small>RAS# to CAS# delay (tRCD)</small> |
<small>11</small> |
<small>RAS# Precharge (tRP)</small> |
<small>11</small> |
<small>Cycle Time (tRAS)</small> |
<small>28</small> |
<small>Command Rate (CR)</small> |
<small>1T</small> |